1. Field of the Invention
This invention relates generally to communication protocols, and more particularly to communication protocols that connect computer systems to peripheral devices.
2. Description of the Related Art
A basic component of a host computer system is the peripheral device. Peripheral devices come in many forms, such as, hard drives, CD-ROMs, optical discs, and the like. To enable communication between the host computer system and its peripheral devices, data transfer protocols such as IDE and SCSI are used. As is well known, the SCSI protocol is designed for high bandwidth and performance demanding environments due to its superior data transfer rates. On the other hand, the IDE protocol is designed to be a lower cost alternative to the SCSI protocol. Thus, computer systems that are designed with a budget in mind tend to implement IDE peripheral devices, but suffer in terms of performance.
FIG. 1 illustrates a typical host computer system 12 that implements peripheral devices 14 and 18. As shown, peripheral device 14 is an internal peripheral device, which can be either IDE or SCSI. Peripheral device 18, on the other hand, is an external device. Because IDE devices implement parallel data transfer buses, IDE peripheral devices are generally manufactured in the form of internal devices. Consequently, in order to connect an external peripheral device, such as device 18 to the host computer system 12, a host adapter needs to be installed into the host computer system 12. To implement external devices, a SCSI host adapter can be connected to the host computer system 12 by way of a PCI bus. The SCSI host adapter can then allow communication over a SCSI bus 16 to the peripheral device 18, which also needs to be a SCSI device. Although, the implementation of SCSI devices can add cost to the system, thus discouraging cost sensitive consumers from implementing external peripheral devices.
In order to maintain cost at a minimum, most computer motherboards come integrated with two IDE connectors. As is well known, each IDE connector can then support a short and bulky IDE parallel cable that itself has two IDE connectors. Each of the two IDE connectors can then connect up to a particular internal IDE peripheral device. For each pair of IDE devices, one device is designated as a master device and the other is designated as a slave device. This designation enables a particular IDE hard drive that is connected to a master connection to be designated as a boot device. Thus, the master IDE device, which is in the form of a hard drive is typically the boot device that contains an operating system (OS) image. Following this implementation, such computer systems can add more internal peripheral devices.
As a result, the IDE protocol provides a low end solution that has limitations on performance such as speed, cable length, and extendibility to external devices. In view of the foregoing, there is a need for a more robust protocol that can deliver improved communication performance, can be extended to external devices, provides for longer and less bulky cable lengths and is a cost sensitive solution that enables the manufacturer of such devices at cost structures that are about equivalent to today""s low end IDE solutions.
Broadly speaking, the present invention fills these needs by providing an advanced serial protocol (ASP) that defines a more robust data transmission environment for communication between host computers and peripheral devices. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, a method, or a computer readable medium. Several inventive embodiments of the present invention are described below.
In one embodiment, a host controller for enabling communication between a host computer and a device over a serial link is disclosed. The host controller includes a bus interface circuit that is connected to a system bus of the host computer. The host controller further includes host controller registers to enable code configuration of the host controller for operation, initialize the device, and send commands to the device. A packet generator/decoder circuit is also provided for generating poll packets to be sent to the device and for sending and receiving packets to or from the device. The host controller also has a serializer/deserializer for converting parallel data received from the bus interface circuit and to be sent over the serial link to the device into serial data and converting serial data received from the serial link to parallel data to be sent to the bus interface circuit and to the host computer.
In another embodiment, a host controller chip integrated into a host adapter is disclosed. The host controller chip is configured to enable communication between a host computer that has the host adapter connected thereto and a peripheral device. A serial cable is configured to interconnect the host adapter to the peripheral device, and the serial cable includes: (a) a first differential pair for data; (b) a second differential pair for strobe; and (c) a pair for ground. The host controller chip includes a PCI bus interface circuit for connecting the host adapter to the host computer, and host controller registers integrated into the host controller chip to enable configuration of the host adapter for operation, initialize the peripheral device, and enable command transmission to the peripheral device over the serial cable. The host controller chip further includes a packet generator/decoder circuit for generating poll packets to be sent to the peripheral device and for sending and receiving packets to and from the peripheral device. A serializer/deserializer circuit is also integrated into the host controller chip for converting parallel data received from the PCI bus interface circuit and to be sent over the serial cable to the peripheral device into serial data and converting serial data received from the serial cable into parallel data to be sent to the PCI bus interface circuit and to the host computer.
In yet a further embodiment, a system for executing data transfers between a host computer and a peripheral device over a serial link is disclosed. The system includes a CPU for setting up a command descriptor block (CDB) with an ATA/ATAPI command and a scatter/gather list in a system memory. A pointer register that is resident in a host controller chip is also provided, and the CPU is configured to write an address of the CDB into the pointer register. A DMA controller is provided for instructing a transfer of the CDB to RAM memory of the host controller chip, and the host controller chip is configured to send the CDB to a peripheral device over a serial physical cable. The host controller chip further being configured to send IN packets to poll the peripheral device for data packets. The device is configured to respond to the poll by sending data packets to the RAM of the host controller chip. A data buffer is also provided and is configured to receive the data packets at the direction of the DMA controller, and the data buffer being pointed to the scatter/gather list in the system memory. The host controller chip is configured to set up an interrupt status to interrupt the CPU indicative of the receipt of the data packets from the peripheral device.
The advantages of the present invention are numerous. Most notably, the ASP bus is specified to be an industry standard extension to the PC architecture which will be a replacement or alternative for the IDE bus. ASP will provide higher speeds and more fault tolerant operations while not requiring a complete change to the current IDE command structure. The ASP provides exceptional ease of use for PC peripheral expansion and is a low-cost solution that supports fast transfer rates. ASP is capable of being integrated in commodity device technology, and provides a standard interface capable of quick diffusion into existing products. ASP is designed to be an extension of the IDE protocol and ATA/ATAPI command set for the attachment of block oriented devices.
ASP is also extendable in terms of the speed that can be achieved. Today, IDE can only operate to 16 MBps (33 MBps is defined but has not yet been used). Some embodiments of the ASP will enable link communication up to about 960 MBps without adversely affecting the protocol. Also, ASP will provide some performance features such as overlapped commands to different devices, DMA transfers only and dynamic allocation of bandwidth to faster devices when needed. Also ASP provides more robust reliability with the inclusion of CRC checking on the data and true plug and play capability.
Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.